1. Field of Invention
The present invention relates to semiconductor technique, and more particularly, to a method for integration of dual metal gates and dual high-k dielectrics in CMOS devices, which may be applied for fabricating a high performance complementary metal-oxide-semiconductor (CMOS) device of the technology generation of 45 nanometers and beyond.
2. Description of Prior Art
As the feature size of the CMOS device is increasingly scaled, it is an inevitable trend for application of high-k (dielectric constant) gate dielectrics and metal gates. The high-k gate dielectric layer has a larger physical thickness at the same equivalent oxide thickness (EOT), which may significantly reduce tunneling current of the gate. However, the high-k gate dielectric layer is not compatible with the conventional polysilicon gate, which may lead to serious Fermi level pinning effects. Therefore, it is necessary that the conventional polysilicon gate be replaced with a novel metal gate. The application of metal gates may eliminate depletion effects of the polysilicon gate, reduce gate resistance and alleviate boron penetration effects, so as to improve reliability of devices. However, there are still some challenges in the integration of the metal gate with the high-k gate dielectric layer, such as thermal stability, interface states, especially the big challenge of the achievement for an appropriately low threshold voltage required by nano CMOS devices due to the Fermi level pinning effects.
Since N-type MOS (NMOS) device and P-type MOS (PMOS) device should have effective work functions at bottom of the conduction band (about 4.1 eV) of Si and at top of the valence band (about 5.2 eV) of Si, respectively, to achieve an appropriate threshold voltage for nano COMS devices. Thus respective suitable metal gates and high-k dielectrics are generally required for NMOS and PMOS devices, which means integration of dual metal gates and dual high-k gate dielectrics is required. The processes for manufacturing the dual metal gates and the dual high-k gate dielectrics are typically very complicated because of processes such as the requirements of “deposition, photolithography, etching, redeposition, rephotolithography, reetching”. Such a process has poor controllability, high manufacturing cost and may not facilitate mass production.